Adjustable timing circuit of an integrated circuit

ABSTRACT

An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay element can include capacitors that are selectively coupled to a propagation path in response to the data stored in the fuse circuits. In one embodiment, data stored in the programmed fuses is copied to volatile latch circuits for use during operation of the timing circuit. The adjustable timing circuit can be provided in any integrated circuit, but is particularly useful in memory devices. The timing system allows for testing and fine-tuning signal processing in the integrated circuits.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. patent application Ser. No.10/931,427, filed Sep. 1, 2004 and titled, “ADJUSTABLE TIMING CIRCUIT OFAN INTEGRATED CIRCUT,” which is a Continuation of U.S. patentapplication Ser. No. 09/648,857, filed Aug. 25, 2000 and titled,“ADJUSTABLE TIMING CIRCUIT OF AN INTEGRATED CIRCUT,” which is commonlyassigned and incorporated by reference in its entirety herein.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and inparticular the present invention relates to adjusting a timing ofcontrol signals.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. There are several different types ofmemory. One type is RAM (random-access memory). This is typically usedas main memory in a computer environment. RAM refers to read and writememory; that is, you can both write data into RAM and read data fromRAM. This is in contrast to ROM, which permits you only to read data.Most RAM is volatile, which means that it requires a steady flow ofelectricity to maintain its contents. As soon as the power is turnedoff, whatever data was in RAM is lost.

Computers almost always contain a small amount of read-only memory (ROM)that holds instructions for starting up the computer. Unlike RAM, ROMcannot be written to. An EEPROM (electrically erasable programmableread-only memory) is a special type non-volatile ROM that can be erasedby exposing it to an electrical charge. Like other types of ROM, EEPROMis traditionally not as fast as RAM. EEPROM comprise a large number ofmemory cells having electrically isolated gates (floating gates). Datais stored in the memory cells in the form of charge on the floatinggates. Charge is transported to or removed from the floating gates byprogramming and erase operations, respectively.

Yet another type of non-volatile memory is a flash memory. A flashmemory is a type of EEPROM that can be erased and reprogrammed in blocksinstead of one byte at a time. Many modern personal computers have theirBIOS stored on a flash memory chip so that it can easily be updated ifnecessary. Such a BIOS is sometimes called a flash BIOS. Flash memory isalso popular in modems because it enables the modem manufacturer tosupport new protocols as they become standardized.

A typical flash memory comprises a memory array that includes a largenumber of memory cells arranged in row and column fashion. Each of thememory cells includes a floating gate field-effect transistor capable ofholding a charge. The cells are usually grouped into blocks. Each of thecells within a block can be electrically programmed on a random basis bycharging the floating gate. The charge can be removed from the floatinggate by a block erase operation. The data in a cell is determined by thepresence or absence of the charge in the floating gate.

A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higherclock speeds than conventional DRAM memory. SDRAM synchronizes itselfwith a CPU's bus and is capable of running at 100 MHZ, about three timesfaster than conventional FPM (Fast Page Mode) RAM, and about twice asfast EDO (Extended Data Output) DRAM and BEDO (Burst Extended DataOutput) DRAM. SDRAM's can be accessed quickly, but are volatile. Manycomputer systems are designed to operate using SDRAM, but would benefitfrom non-volatile memory.

Integrated circuits, such as memory devices, include internal signalprocessing circuits. That is, one or more signals are processed togenerate additional internal signals. The timing between these signalscan be critical to the operation of the integrated circuit. Because theinitial design of internal circuitry is often changed during debugging,the integrated circuit masks must be changed. The economic and timedelays of changing the masks are not desirable. Further, structurallimitations often result in a compromised solution to problemsidentified during testing.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art forsignal processing and timing circuitry that can be adjusted during andafter testing.

SUMMARY OF THE INVENTION

The above-mentioned problems with integrated circuits and other problemsare addressed by the present invention and will be understood by readingand studying the following specification.

In one embodiment, an integrated circuit timing circuit comprises aprogrammable non-volatile fuse circuit, and an adjustable delay elementcoupled to the programmable non-volatile fuse circuit. The delay elementhas a plurality of propagation times selectable in response to theprogrammable non-volatile fuse circuit.

In another embodiment, an integrated circuit timing circuit comprises aprogrammable non-volatile fuse circuit, a volatile latch circuit coupledto the non-volatile fuse circuit, and a plurality of adjustable delayelements coupled to the volatile latch circuit. Each of the plurality ofadjustable delay elements comprises a propagation path, and a pluralityof capacitors selectively coupled to the propagation paths of theplurality of adjustable delay elements in response to the volatile latchcircuit.

A memory device, in an embodiment, comprises an array of memory cells,access circuitry to generate a plurality of memory array access signals,and an adjustable timing circuit coupled to the access circuitry. Theadjustable timing circuit comprises a programmable non-volatile fusecircuit, and an adjustable delay element coupled to the programmablenon-volatile fuse circuit. The delay element has a plurality ofpropagation times selectable in response to the programmablenon-volatile fuse circuit.

A method of adjusting a signal timing circuit is provided. The methodcomprises programming a non-volatile fuse circuit, and selecting asignal propagation time length in response to the programmednon-volatile fuse circuit.

A method is provided to test a memory device having a signal propagationpath. The method comprises programming a plurality of non-volatile fusesto store first data, selectively coupling one or more capacitors to thepropagation path in response to the first data to provide a firstpropagation path delay time, and testing the memory using the firstpropagation path delay time. The plurality of non-volatile fuses arealso programmed to store second data, and one or more capacitors areselectively coupled to the propagation path in response to the seconddata to provide a second propagation path delay time. The memory is thentested using the second propagation path delay time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory incorporating the presentinvention;

FIG. 2 is an interconnect diagram of one embodiment of the memory ofFIG. 1;

FIG. 3 a block diagram of an adjustable timing circuit of the presentinvention;

FIG. 4 is a schematic diagram of another an adjustable timing circuit ofthe present invention;

FIG. 5 is a timing diagram of the operation of the circuit FIG. 4;

FIG. 6 is another timing diagram of the operation of the circuit FIG. 4;

FIG. 7 is another timing diagram of the operation of the circuit FIG. 4;and

FIG. 8 is a more detailed schematic of an adjustable delay circuit of anembodiment of a present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that logical, mechanical and electricalchanges may be made without departing from the spirit and scope of thepresent invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the claims.

Referring to FIG. 1, a block diagram of one embodiment of the presentinvention is described. A memory device 100 is coupled to a processor200. The memory device 100 includes an array of non-volatile flashmemory cells 102. The array is arranged in a plurality of addressablebanks. In one embodiment, the memory contains four memory banks 104,106, 108 and 110. Each memory bank contains addressable sectors ofmemory cells. The data stored in the memory can be accessed usingexternally provided location addresses received by address register 112.The addresses are decoded using row address multiplexer circuitry 114.The addresses are also decoded using bank control logic 116 and rowaddress latch and decode circuitry 118. To access an appropriate columnof the memory, column address counter and latch circuitry 120 couplesthe received addresses to column decode circuitry 122. Circuit 124provides input/output gating, data mask logic, read data latch circuitryand write driver circuitry. Data is input through data input registers126 and output through data output registers 128. Command executionlogic 130 is provided to control the basic operations of the memorydevice. A state machine 132 is also provided to control specificoperations performed on the memory arrays and cells. A status register134 and an identification register 136 can also be provided to outputdata. The command circuit 130 and/or state machine 132 can be generallyreferred to as control circuitry to control read, write, erase and othermemory operations.

FIG. 2 illustrates an interconnect pin assignment of one embodiment ofthe present invention. The memory package 150 has 54 interconnect pins.The pin configuration is substantially similar to available SDRAMpackages. Two interconnects specific to the present invention are RP#152 and Vccp 154. Although the present invention may share interconnectlabels that are appear the same as SDRAM's, the function of the signalsprovided on the interconnects are described herein and should not beequated to SDRAMs, unless set forth herein. It will be appreciated thatthe present invention is not limited to a specific packageconfiguration.

Prior to describing the operational features of the memory device, amore detailed description of the interconnect pins and their respectivesignals is provided. The input clock connection is used to provide aclock signal (CLK). The clock signal can be driven by a system clock,and all synchronous flash memory input signals are sampled on thepositive edge of CLK. CLK also increments an internal burst counter andcontrols the output registers.

The input command input connections for RAS#, CAS#, and WE# (along withCAS#, CS#) define a command that is to be executed by the memory, thetiming of internal circuitry coupled to one or more of these inputs canbe adjusted as described in detail below. Address inputs 133 areprimarily used to provide address signals. In the illustrated embodimentthe memory has 12 lines (A0-A11). Other signals can be provided on theaddress connections, as described below. The address inputs are alsoused to provide an operating code. Address lines A0-A11 are also used toinput mode settings during a mode register load operation.

Bank address input connections, BA0 and BA1 define which bank an active,read, write, or block protect command is being applied. The DQ0-DQ15connections are data bus connections used for bi-directional datacommunication. The VCC connection provides a power supply, such as 3V. Aground connection is provided through the Vss connection. Anotheroptional voltage is provided on the VCCP connection. The VCCP connectioncan be tied externally to VCC, and sources current during deviceinitialization, write and erase operations. That is, writing or erasingto the memory device can be performed using a VCCP voltage, while allother operations can be performed with a VCC voltage. The Vccpconnection is coupled to a high voltage switch/pump circuit 145.

One embodiment of the memory is a nonvolatile, electricallysector-erasable (Flash), programmable read-only memory containing67,108,864 bits organized as 4,194,304 words by 16 bits. Otherpopulation densities are contemplated, and the present invention is notlimited to the example density. Each memory bank is organized into fourindependently erasable blocks (16 total). To ensure that criticalfirmware is protected from accidental erasure or overwrite, the memorycan include sixteen 256K-word hardware and software lockable blocks. Thememory's four-bank architecture supports true concurrent operations. Ingeneral, the synchronous flash memory is configured similar to amulti-bank DRAM that operates at low voltage and includes a synchronousinterface.

The memory cells of the above flash memory are floating gatetransistors. Floating gate transistors are field-effect transistors(FET) having an electrically isolated (floating) gate that controlselectrical conduction between source and drain regions. Data isrepresented by charge stored on the floating gate and the resultingconductivity obtained between source and drain regions. A programmedmemory cell has a higher threshold voltage than an erased memory cell.

For example, a floating gate memory cell can be formed in a P-typesubstrate with an N-type diffused source region and an N-type draindiffusion formed in the substrate. The spaced apart source and drainregions define an intermediate channel region. A floating gate,typically made of doped polysilicon, is located over the channel regionand is electrically isolated from the other cell elements by oxide. Forexample, a thin gate oxide can be located between the floating gate andthe channel region. A control gate is located over the floating gate andcan also be made of doped polysilicon. The control gate is separatedfrom the floating gate by a dielectric layer.

Conventionally, a flash cell is programmed by charging the floating gateof the flash cells. The charge is drawn from the flash cells' channelregions into the floating gates by applying relatively highdrain-to-source and gate-to-source voltage pulses to the flash cells.During programming, the flash cells generate hot electrons in thechannel current that travel at a saturated or maximum velocity, and thushave high energy. Hot electrons arise in the channels of flash cellsbecause the drain-to-source voltages are sufficiently high, and theflash cells' gate lengths are sufficiently small. Hot electrons in thechannel current form a programming current used to program the flashcell. The programming current is the flow of hot electrons from a flashcell channel region into its floating gate. Hot electrons can onlysurmount the energy barrier separating the floating gate and the channelwhen the energy barrier is reduced by a sufficiently high gate-to-sourcevoltage, such as when the flash cell operates in the linear region. Toerase a memory cell, the charge stored on the floating gate is removed.

Signal processing, such as array access signals, in the memory device iscontrolled using adjustable timing circuitry, explained below. Thecircuitry includes adjustable delay elements and programmablenon-volatile fuses. The fuses can be flash memory cells as describedabove. The data stored in the non-volatile fuses can be coupled tovolatile latches for use during integrated circuit operation. That is,reading a volatile latch can often be performed faster than reading anon-volatile cell.

The present invention provides a non-volatile ‘fuse’ circuit 190 thatcan be selectively programmed to control timing circuits in anintegrated circuit. In one embodiment, the fuse elements 190 are coupledto programmable delay circuits 192 and 194 as illustrated in FIG. 3. Thedelay elements are arranged in a timing chain and are coupled to latchcircuits 196. The latch circuits can be set/re-set latches.

Referring to FIG. 4, another embodiment of the present invention isdescribed. Non-volatile fuse circuitry 200 is coupled to delay elements204, 206, 208, 210 and 212. Delay element 204 is coupled to fuses 3, 4and 5. Each of the delay elements are coupled to three fuses. Forexample, delay element 212 is coupled to fuses 15, 16 and 17. The delayelements are coupled in series between input 250 and latch circuitry220. Other circuitry may be coupled to the delay elements. For example,an inverter 221 and a NAND gate 224 are coupled with delay element 202to form a one-shot signal generator. The output signals from several ofthe delay elements are coupled to multiple latch circuits 222, 224 and226. FIGS. 5, 6 and 7 illustrate timing diagrams of the operation of thecircuit of FIG. 4. By adjusting the fuse elements 0-17 of the fusecircuit 200, the delay times of the series coupled elements are adjustedto control a propagation time of the delay chain.

In FIG. 5, all of the timing elements have a delay of two time units.That is, a signal transition received on an input of a delay element iscoupled to an output of the delay element in two time units. Note, inthe following timing diagram, the delay time of the logic gates isassumed to be zero. At T0 an input signal on node 250 transitions from alow state to a high state. The signal is coupled though NOR gate 252 andNAND gate 224 to pull node TPIN high (Reset signal is low). Delayelement 202 delays the signal from the second input of NAND gate 224 fortwo units. After two units, the output of the NAND gate transitions to alow state, time T2. Thus, TPIN is high from TP0 to TP2. Because thedelay elements are all set to a common delay time, the two-unit signalis rippled through the delay chain. The first latch circuit 222 iscoupled to signals T0 and the output of delay 208 (TP2). As such, TOUT0transitions high at T2 and the latch is reset at T6 in response to TP2.The second latch circuit 224 is coupled to signals T0 and TP3 (delay210). As such, TOUT1 transitions high at T2 and latch 224 is reset at T8in response to TP3. Finally, the third second latch circuit 226 iscoupled to signals TP1 and TP4 (output of delay 212). Thus, TOUT2transitions high at T4 and the latch is reset at T10 in response to TP4.

FIG. 6 illustrates a timing diagram of the circuit of FIG. 4 whereinsome of the delay element times are adjusted. Delay elements 206 and 212are adjusted so that they have a delay of one time unit and delayelements 208 and 210 are adjusted to have a delay of three time units.As illustrated, the TP1 and TP4 signals transition to a high state onetime unit following the TP0 and TP3 signal transitions, respectively.Likewise, the TP2 and TP3 signals transition to a high state one timeunit following the TP1 and TP2 signal low transitions, respectively. Assuch, the TOUT1 signal resets at a later time. That is, TOUT1transitions to a low state at T9 instead of T8. The set transition ofTOUT2 has been adjusted to transition to a high state at T3 instead ofT4.

Another embodiment of the present invention is illustrated in FIG. 7where the non-volatile fuse circuit has been programmed to change thedelay element times. Here only delay element 206 has been adjusted sothat it has a delay of three time units. As illustrated, the TP1 signaltransitions to a high state three time units following the TP0 signalhigh transition. As such, the TOUT0 signal resets at a later time. Thatis, TOUT0 transitions to a low state at T7 instead of T6. Likewise, bothtransitions of the TOUT2 signal are shifted out by one time unit. Also,TOUT1 is reset at T9 instead of T8.

FIG. 8 illustrates two series coupled delay elements 280 and 290. Eachof the delay elements has three input signals to select a delay time.Delay element 280 is coupled to fuses 0, 1 and 2, provided on nodes 282,284 and 286, respectively. The delay times are controlled by couplingone or more capacitors 300-305 to a signal path of the delay elements280 and 290. That is, a capacitor can be selectively coupled to seriescoupled inverters 310 in response to latches 320. Latches 320 arevolatile and can be cross-coupled inverters as illustrated. When thelatch is programmed to store a logic one, the n-channel transistor 330couples capacitor 300 to the signal propagation path 340 between input350 and output 360. Likewise, the transistor is turned off when thelatch is programmed as a logic zero. The latch circuit is selectivelycoupled to a non-volatile fuse circuit 200 via load transistors 365. Assuch, data stored in the non-volatile fuse elements is copied to thevolatile latch when the load transistors are activated via Load signalon node 370. Table 1 illustrates logic states of the six fuses andrepresentative time delays units (assuming zero delay due to propagationthrough the inverter series). It will be appreciated that the delayunits of the series coupled delay elements are cumulative. For example,a delay time of 3 delay units for each delay element results in a totaldelay time of six delay units. TABLE 1 Delay Fuse 0 Fuse 1 Fuse 2 Fuse 3Fuse 4 Fuse 5 Units 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 11 2 0 0 0 1 0 0 1 0 0 0 1 0 1 2 0 0 0 1 1 1 3 0 0 1 0 0 0 1 0 1 0 0 0 01 0 1 1 0 0 0 2 1 0 0 0 0 0 1 1 0 1 0 0 0 2 1 1 1 0 0 0 3

The above described embodiments and operating examples should not beconstrued as limiting the present invention. One skilled in the art,with the benefit of the present description, will understand thatchanges in the circuitry can be made without departing from the presentinvention. For example, more complicated latch circuitry can be coupledto the delay element(s). Likewise, the input circuitry can be modifiedto receive multiple input signals. One application of the presentinvention is in a memory device to adjust timing of signals used toaccess a memory array. For example, a column address strobe signal canbe used in a memory to trigger a series of events during a readoperation. The timing of these events can be adjusted using the presentinvention.

CONCLUSION

An adjustable timing circuit has been described. The timing circuitincludes non-volatile programmable fuses and adjustable delay elements.In one embodiment, the data stored in the programmed fuses is copied tovolatile latch circuits for use during operation of the timing circuit.The delay element can include capacitors that are selectively coupled toa propagation path in response to the data stored in the fuse circuits.The adjustable timing circuit can be provided in any integrated circuit,but is particularly useful in memory devices. The timing system allowsfor testing and fine-tuning signal processing in the integratedcircuits.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A method for testing a memory device comprising a signal propagationpath, the method comprising: programming a plurality of non-volatilefuses to store first data; selectively coupling one or more capacitorsto the propagation path in response to the first data to provide a firstpropagation path delay time and an edge position for edges of signals;testing the memory using the first propagation path delay time;programming the plurality of non-volatile fuses to store second data;selectively coupling one or more capacitors to the propagation path inresponse to the second data to provide a second propagation path delaytime; and testing the memory using the second propagation path delaytime.
 2. The method of claim 1 wherein the memory device is a flashmemory having an array of floating gate memory cells and the pluralityof non-volatile fuses comprise floating gate transistors.
 3. The methodof claim 1 further comprising: copying the first data from the pluralityof non-volatile fuses to a plurality of latches before selectivelycoupling one or more capacitors to the propagation path in response tothe first data; and copying the second data from the plurality ofnon-volatile fuses to the plurality of latches before selectivelycoupling one or more capacitors to the propagation path in response tothe second data.
 4. The method of claim 1 wherein selectively couplingcomprises switching the one or more capacitors to the propagation pathin response to a volatile latch circuit.
 5. The method of claim 1wherein programming comprises biasing the plurality of non-volatilefuses with a voltage greater than V_(CC).
 6. A method for testing afloating gate memory array comprising a signal propagation path havingan adjustable delay, the method comprising: programming a plurality ofnon-volatile fuses to store first data; selectively creating a firstpropagation path delay time and an edge position for edges of signals inresponse to the first data; and testing the memory using the firstpropagation path delay time and the edge positions.
 7. The method ofclaim 6 wherein selectively creating the first propagation pathcomprises switching at least one capacitor to the propagation path inresponse to the first data.
 8. The method of claim 6 wherein the firstpropagation path delay time is one to three units of time.
 9. The methodof claim 7 wherein switching at least one capacitor comprises switchingone of three capacitors.
 10. The method of claim 6 and further includingadjusting the first propagation path delay time in response to a failedtest.
 11. The method of claim 10 wherein a failed test comprises a timeinterval between at least two memory signals being too short.
 12. Amethod for testing a flash memory device comprising a signal propagationpath, the method comprising: programming a plurality of non-volatilefuses to store first data; selectively coupling one or more capacitorsto the signal propagation path in response to the first data to providea first propagation path delay time and an edge position for edges ofsignals; and testing the memory using the first propagation path delaytime.
 13. The method of claim 12 and further including changing thefirst propagation path delay time by increasing the quantity ofcapacitors coupled to the signal propagation path.
 14. The method ofclaim 12 and further including changing the first propagation path delaytime by decreasing the quantity of capacitors coupled to the signalpropagation path.
 15. The method of claim 12 wherein selectivelycoupling comprises the non-volatile fuses turning on a predeterminedquantity of transistors in response to the first data.
 16. The method ofclaim 15 wherein each of the predetermined quantity of transistorscouples a capacitor to the signal propagation path.
 17. The method ofclaim 12 wherein the first data indicates the amount of time delay toadd to the signal propagation path.
 18. The method of claim 12 whereinthe first data comprises a predetermined pattern that selectively turnson transistors, each transistor coupling a capacitor to the signalpropagation path.